Implementation of an Efficient FBMC Transceiver using N-IFFT and Pipelined R- DFT on FPGA

Manohar K. ; Naveen Kumar G. N.;

This paper evaluates the implementation aspects of Filter Bank Multicarrier (FBMC), a recently investigated multicarrier
modulation scheme. FBMC signals can easily meet the Adjacent Channel Leakage Ratio (ACLR) requirements of Cognitive
Radio (CR) systems. The paper presents a novel, low complexity transmitter structure, which can be efficiently, implemented
using an FPGA, and which can further reduce the signal processing complexity of the FBMC transmitter. The complexity of
the proposed technique is half of that of a conventional FBMC implementation. The paper also introduces a novel receiver
architecture based on a stable Recursive Discrete Fourier Transform (R-DFT) providing continuous time frequency analysis
for spectral sensing Filter bank multicarrier (FBMC) scheme is currently under investigation as a viable candidate for radio
access replacing the current orthogonal frequency division multiplexing (OFDM). This is due to the possibility of higher
spectral efficiency and less susceptibility to synchronization errors, in this case accompanied without the cyclic prefix. The
paper compares the computational complexity of different transceiver architectures and gives suggestions for the method
most suitable for FPGA implementation